When purchasing a silicon carbide wafer for epitaxial growth, specifying only the wafer diameter, polytype and doping type is not enough. The wafer’s off-axis angle, also known as the miscut angle, can significantly affect step-flow growth, polytype stability, surface morphology, defect propagation and final device yield.

For 4H-SiC wafers, three commonly discussed orientations are:

• 0° or nominally on-axis
• 4° off-axis
• 8° off-axis

These angles are not interchangeable. A 0° wafer is not automatically more accurate, while an 8° wafer is not automatically better for epitaxy. Each angle creates a different surface-step structure and must be matched to the epitaxial process and device application.

This guide explains how 0°, 4° and 8° SiC wafer miscut angles affect epitaxy and provides an RFQ checklist for selecting the correct substrate.

What Is the Off-Axis Angle of a SiC Wafer?

A SiC crystal has defined crystallographic planes and directions. For a standard C-plane 4H-SiC wafer, the nominal surface is perpendicular to the crystal’s c-axis, represented by the (0001) plane.

An on-axis wafer is cut approximately parallel to this basal plane.

An off-axis wafer is intentionally sliced at a small angle away from the exact basal plane, normally toward a specified crystallographic direction such as:

4° toward ⟨11-20⟩

The intentional tilt creates a surface containing atomic terraces separated by steps. These steps provide preferred sites for atoms arriving during epitaxial growth.

The off-axis specification therefore includes two separate items:

1. Off-axis angle
2. Off-axis direction

A specification stating only “4° off-axis” is incomplete if the crystallographic direction and angular tolerance are not included.

Why SiC Epitaxy Uses an Intentional Miscut

Silicon carbide exists in many crystal structures called polytypes. Common examples include 3C-SiC, 4H-SiC and 6H-SiC.

During homoepitaxial growth, the objective is normally to reproduce the substrate’s polytype. For example, a 4H-SiC substrate should produce a 4H-SiC epitaxial layer.

The atomic steps on an off-axis surface help the arriving silicon and carbon species follow the stacking sequence of the underlying crystal. This mechanism is called step-controlled epitaxy or step-flow growth.

Published research confirms that 4H-SiC epitaxy commonly uses 4° off-angle substrates to improve step-flow growth and maintain polytype stability. Materials research on 3C inclusion formation

The general relationship is:

• Smaller miscut angle: wider terraces and lower step density
• Larger miscut angle: narrower terraces and higher step density

However, increasing the step density also changes step bunching, surface roughness, defect behavior and material utilization.

0° On-Axis SiC Wafers

Surface Characteristics

A nominally on-axis SiC wafer has a surface close to the exact (0001) basal plane. Its terraces are wider and its natural step density is lower than that of 4° or 8° wafers.

“On-axis” does not always mean exactly 0.000°. Real wafers may still contain a small residual misorientation caused by crystal curvature, slicing accuracy, wafer bow and polishing.

Therefore, an RFQ should state an angular tolerance, such as:

On-axis (0001) ±0.5°

For demanding research, a tighter tolerance or full-wafer orientation map may be necessary.

Advantages of 0° Wafers

Potential advantages include:

• Better boule material utilization
• Less crystal material lost through angled slicing
• Suitability for semi-insulating RF substrates
• Suitability for selected GaN-on-SiC processes
• Reduced replication of certain basal-plane dislocations under specific growth conditions
• Availability for research into low-off-axis or on-axis homoepitaxy

Challenges of 0° Homoepitaxy

With fewer surface steps, atoms have fewer preferred step-edge incorporation sites. Two-dimensional nucleation can become more likely if the process is not carefully controlled.

For 4H-SiC homoepitaxy, this may lead to:

• 3C-SiC inclusions
• Polytype instability
• Triangular defects
• Surface islands
• Non-uniform step formation
• Reduced usable device area

Research on nominally on-axis Si-face 4H-SiC demonstrated that high-quality homoepitaxy is possible, but controlling 3C-SiC inclusions remains an important processing challenge. On-axis 4H-SiC epitaxy study

Modern reactor design, in-situ etching, temperature control, precursor ramping and C/Si ratio optimization can improve on-axis growth. Nevertheless, an epitaxial recipe developed for 4° wafers cannot simply be transferred to 0° wafers without process development.

Typical Applications

On-axis 4H-SiC wafers may be selected for:

• High-purity semi-insulating SiC substrates
• GaN-on-SiC RF epitaxy
• Microwave and radar device substrates
• Optical and research applications
• Alternative homoepitaxial growth processes
• Basal-plane-dislocation research
• Customized non-standard epitaxial structures

The correct angle for GaN-on-SiC should be confirmed with the GaN epitaxy provider because AlN nucleation, polarity and reactor conditions can change the preferred miscut.

4° Off-Axis SiC Wafers

Why 4° Has Become a Common Choice

A 4° off-axis 4H-SiC wafer provides a practical balance between step density, epitaxial process stability and substrate manufacturing cost.

The surface contains sufficient steps to support step-flow growth while avoiding some of the material-utilization disadvantages associated with a larger 8° cut.

A common specification for conductive 4H-SiC power-device substrates is:

4° toward ⟨11-20⟩ ±0.5°

The exact direction and tolerance should still be confirmed for every process.

Advantages of 4° Wafers

A properly prepared 4° substrate can provide:

• Stable 4H polytype replication
• Reliable step-flow epitaxy
• Compatibility with established power-device processes
• Good control of epitaxial thickness and doping
• Lower material loss than an 8° offcut
• Broad availability for N-type 4H-SiC
• Compatibility with SiC MOSFET and Schottky diode production

Research has demonstrated high-growth-rate, thick 4H-SiC epitaxial layers with controlled morphology on 4° off-axis substrates when temperature, surface chemistry, C/Si ratio and pre-growth etching are optimized. 

Potential Defects on 4° Wafers

A 4° off-axis angle does not eliminate epitaxial defects. Possible issues include:

• Step bunching
• Triangular defects
• Carrot defects
• Basal-plane dislocations
• Threading edge or screw dislocations
• Surface scratches transferred into the epitaxial layer
• Local polytype inclusions
• Edge-related thickness non-uniformity

The final defect density depends on both the substrate and the growth process. Surface preparation, hydrogen etching, growth rate, pressure, temperature and precursor ratio all influence the result.

Typical Applications

A 4° off-axis 4H-N SiC wafer is commonly considered for:

• SiC MOSFETs
• Schottky barrier diodes
• Junction barrier Schottky diodes
• PiN diodes
• High-voltage power devices
• Electric vehicle inverters
• Onboard chargers
• Industrial power supplies
• Renewable-energy converters
• Thick SiC epitaxial layers

For most standard conductive 4H-SiC power-device projects, 4° is the first orientation that buyers should evaluate.

8° Off-Axis SiC Wafers

Surface Characteristics

An 8° off-axis wafer has approximately twice the nominal inclination of a 4° wafer. It therefore presents a higher density of surface steps and narrower terraces.

Historically, 8° off-axis substrates were widely used to provide strong step-flow conditions and reliable polytype replication.

Advantages of 8° Wafers

Potential advantages include:

• High surface-step density
• Strong step-flow growth
• Reduced risk of unwanted two-dimensional nucleation
• Good polytype replication under compatible growth conditions
• Compatibility with legacy epitaxial processes developed around 8° substrates
• Suitability for specialized research or custom device structures

Limitations of 8° Wafers

A larger off-axis angle can introduce commercial and processing disadvantages:

• Greater boule material loss during angled slicing
• Higher substrate manufacturing cost
• More demanding angle and direction control
• Increased sensitivity to step bunching
• Possible surface morphology differences
• Reduced interchangeability with modern 4° epitaxial recipes
• Lower standard availability from some suppliers

The larger cut angle means fewer wafers may be obtained from a given crystal boule. This disadvantage becomes more important as wafer diameter increases.

Research comparing off-axis approaches has identified 4° substrates as a cost-saving alternative to 8° substrates while maintaining effective step-flow growth.

Typical Applications

An 8° off-axis SiC wafer may be appropriate for:

• Existing epitaxial reactors qualified for 8° material
• Legacy device production
• Specialized thick epitaxial structures
• Step-flow and polytype research
• Customized 4H-SiC or 6H-SiC epitaxy
• Processes where higher step density is specifically required

A buyer should not switch from 8° to 4° only to reduce substrate cost without first qualifying the epitaxial process.

0° vs 4° vs 8° SiC Wafer Comparison

The table provides general selection guidance. Actual performance depends on polytype, face polarity, growth method, wafer size and epitaxial recipe.

How Miscut Angle Affects Device Yield

1. Polytype Inclusions

Unwanted 3C-SiC inclusions can create electrically defective regions and reduce the usable die area.

On-axis growth is particularly sensitive to polytype nucleation, while 4° and 8° surfaces provide more steps for maintaining the 4H stacking sequence.

2. Surface Morphology

A smooth epitaxial surface is essential for photolithography, gate-oxide formation and device uniformity.

Incorrectly matched offcut and growth conditions can produce:

• Step bunches
• Triangular defects
• Surface pits
• Hillocks
• Rough terraces
• Local thickness variation

3. Basal-Plane Dislocations

Basal-plane dislocations are important for bipolar SiC devices because they can contribute to stacking-fault expansion and forward-voltage degradation.

Off-axis growth can replicate BPDs from the substrate into the epitaxial layer. Modern processes attempt to convert BPDs into less harmful threading edge dislocations or prevent their propagation.

4. Epitaxial Doping Uniformity

Step density influences how nitrogen and other dopants are incorporated during growth. Changing the off-axis angle may therefore require adjustments to gas flow, temperature and C/Si ratio to maintain target doping.

5. Wafer-Level Uniformity

The actual off-angle may vary from center to edge because of crystal-plane curvature and wafer geometry. This can cause local changes in step structure across the wafer.

For larger wafers or demanding production, buyers may request:

• Full-wafer off-angle mapping
• Center and edge measurements
• Offcut direction mapping
• X-ray orientation reports
• Wafer bow and warp data

6. Substrate Cost and Die Economics

A larger off-axis angle may improve certain epitaxial conditions but reduce the number of substrates that can be sliced from a boule.

The lowest-defect epitaxial result does not necessarily produce the lowest total device cost. Buyers must consider:

• Substrate price
• Epitaxial yield
• Usable area
• Device yield
• Reliability
• Process qualification cost

Si-Face vs C-Face: Another Critical Specification

The off-axis angle must not be evaluated separately from wafer polarity.

A SiC wafer can be processed on:

• Si-face: (0001)
• C-face: (000-1)

Most commercial 4H-SiC power-device epitaxy uses the Si-face. C-face material may be used for specialized epitaxy, research, graphene formation or processes requiring different surface chemistry.

Si-face and C-face surfaces can behave differently during:

• Hydrogen etching
• Step formation
• Dopant incorporation
• Oxidation
• Polytype nucleation
• Surface reconstruction

An RFQ should therefore state both the face and the off-axis specification.

Application-Based Selection Guide

4H-SiC MOSFET or Schottky Diode

Recommended starting point:

• 4H-N conductive SiC
• Si-face
• 4° toward ⟨11-20⟩
• Epi-ready CMP surface

GaN-on-SiC RF Device

Recommended starting point:

• High-purity semi-insulating 4H-SiC
• On-axis or low-miscut orientation
• Orientation confirmed with the GaN epitaxy provider
• Tight resistivity and surface-defect control

Existing 8° Epitaxial Process

Recommended starting point:

• Maintain the qualified 8° angle and direction
• Compare 4° material only through a controlled qualification lot
• Retune the epitaxial recipe before production conversion

On-Axis 4H-SiC Homoepitaxy Research

Recommended starting point:

• Nominal 0° Si-face or C-face
• Tight full-wafer orientation control
• Dedicated surface preparation
• Optimized nucleation and precursor ramping
• Detailed 3C inclusion mapping

SiC Wafer Off-Axis RFQ Checklist

Example RFQ for a 4H-N Power-Device SiC Wafer

Application: SiC MOSFET epitaxial growth
Material: 4H-SiC
Conductivity: N-type
Diameter: 150 mm
Orientation: 4° off-axis toward ⟨11-20⟩
Angle Tolerance: ±0.5°
Surface: Si-face CMP, epi-ready
Backside: C-face optical polish
Thickness: According to device-fab handling requirements
Resistivity: Defined production range
TTV: Buyer-defined maximum
Bow/Warp: Buyer-defined maximum
Surface Roughness: Ra below the agreed CMP limit
Defects: MPD, BPD, TSD and edge-defect limits required
Inspection: X-ray orientation, surface scan and geometry report
Quantity: 5 wafers for qualification, followed by production order

Frequently Asked Questions

Is 4° always the best off-axis angle for 4H-SiC?

No. A 4° off-axis angle is widely used for conductive 4H-SiC power-device epitaxy, but semi-insulating RF substrates, legacy processes and specialized research may require 0°, 8° or another angle.

Can a 0° SiC wafer be used for epitaxy?

Yes, but on-axis homoepitaxy generally requires a dedicated growth process to control polytype nucleation, 3C-SiC inclusions and surface morphology.

Why did the industry move from 8° to 4° for many power applications?

A 4° offcut provides sufficient step density for stable epitaxy while improving boule utilization and reducing material cost compared with a larger 8° cut.

Is off-axis direction as important as the angle?

Yes. Two wafers with the same 4° angle but different offcut directions may show different step structures and epitaxial behavior. Always specify both angle and direction.

What angle is normally used for semi-insulating SiC?

Semi-insulating 4H-SiC is frequently supplied on-axis for RF and GaN-on-SiC applications. However, 4° and 8° options may be available for customized epitaxial processes.

Can a 4° wafer replace an 8° wafer directly?

Not without qualification. The epitaxial recipe may require changes to temperature, growth rate, pressure, pre-etching and precursor ratios.

Conclusion

The SiC wafer off-axis angle is a functional epitaxial parameter rather than a simple dimensional tolerance.

A 0° wafer offers high material utilization and can be suitable for semi-insulating RF substrates or specialized homoepitaxy, but it requires careful control of polytype nucleation.

A 4° off-axis wafer provides a strong balance between step-flow stability, cost and production compatibility, making it a common choice for conductive 4H-SiC power devices.

An 8° off-axis wafer provides high step density and remains valuable for qualified legacy processes and specialized epitaxial growth, although it may increase material cost and step-bunching sensitivity.

Before requesting a quotation, buyers should confirm:

• Device application
• Polytype and conductivity
• Si-face or C-face
• Off-axis angle and direction
• Angular tolerance
• Surface finish
• Geometry and defect limits
• Epitaxial process compatibility

The best SiC wafer is not the one with the largest or smallest miscut angle. It is the wafer whose orientation, surface and defect specifications match the intended epitaxial process.

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